| Name |
SETO Kenshu |
| Official Title |
Lecturer |
| Affiliation |
Electrical, Electronics and Communication Engineering |
| E-mail |
kseto@tcu.ac.jp |
| Web |
- http://www.risys.gl.tcu.ac.jp/Main.php?action=profile&type=detail&tchCd=5001681
|
| Profile |
My specialty is VLSI design methodology. I am interested in research on high-level synthesis and hardware/software codesign. |
| Research Field(Keyword & Summary) |
- High-level synthesis, Hardware-Software codesign, VLSI
High-level synthesis, Hardware-Software codesign, VLSI
|
| Representative Papers |
- (1) Scalar replacement in the presence of multiple write accesses for accelerator design with high-level synthesis, DATE 2021, 2021
- (2) Shift register initialization in scalar replacement for reducing code size, IPSJ Transactions on System LSI Design Methodology, 2020
- (3) Small Memory Footprint Neural Network Accelerators, ISQED, 2019
- (4) Scalar replacement with circular buffers, IPSJ Transactions on System LSI Design Methodology, 2019
- (5) Scalar replacement with polyhedral model, IPSJ Transactions on System LSI Design Methodology, 2018
|
| Grant-in-Aid for Scientific Research Support: Japan Society for Promotion of Science (JSPS) |
https://nrid.nii.ac.jp/en/nrid/1000010420241/ |
| Recruitment of research assistant(s) |
No |
| Affiliated academic society (Membership type) |
IEEE, IPSJ, IEICE |
| Education Field (Undergraduate level) |
Digital design |
| Education Field (Graduate level) |
Digital design |
