Name MITANI Yuichiro
Official Title Professor
Affiliation Electrical, Electronics and Communication Engineering, Faculty of Science and Engineering
Profile Yuichiro Mitani has been with Corporate R&D Center, Toshiba Corporation (~2018), and Memory R&D Center, KIOXIA Corporation (~2020). In these companies, he engaged the research of the reliability mechanisms for CMOS and flash memory devices. Especially, his research focused on the degradation of dielectrics/semiconductor heterointerface under electrical stressing. This strongly correlates to the reliability of semiconductor devices. For instance, hydrogen-bond breakage at dielectrics/silicon interfaces by injected energetic carriers (electrons or holes) invokes not only the degradation of device performance but also the device failures. Therefore, understanding the mechanisms of bond breakage at heterointerface and improvement of interface structures are essentially important. His specialty and research interests cover characterization and process engineering of CMOS and nonvolatile memory devices, and the device reliabilities. Now, based on his expertise, he starts the research on highly reliable emerging memory technologies for appling to IoT and AI devices.
Research results are clarified through presentations at international conferences and publications in journals, including invited talk and papers.
Research Field(Keyword & Summary)
  1. Reliability physics on nano-electronic devices

    The reliabilities (especially, the time-dependent long-term reliabilities) of nano-electronic devices are indispensable for safe and secure of the end users. In order to realize the highly reliable devices, understanding physics of deterioration under operation is essentially important. We are trying to make physical model of the device reliability from physical analysis and electrical measurements. We focus on the interface and bulk structures of the dielectric films, which is one of the key component of nano-electric devices.

  2. Emerging memories

    Many new materials have been studied over the last decade to determine the optimal materials and device structures for the emerging memories. We are focusing on FTJ (ferroelectric tunnel junction) memory and nano-carbon (e.g., fluorinated graphene) memory. With certain dynamics, these devices can also be used either as synapses or neurons in a neuromorphic computing system. From the physical analysis, electrical measurements, we are trying to fabricate these emerging memory devices based on understanding physical mechanisms behind the phenomena.

Representative Papers
  1. (1) “Investigation of Switching-Induced Local Defects in Oxide-Based CBRAM Using Expanded Analytical Model of TDDB,” IEEE Transactions on Electron Devices, Vol. 66, No. 5, pp. 2165-2171 (2019).
  2. (2) “Evaluation of electron traps in SiNx by discharging current transient spectroscopy: Verification of validity by comparing with conventional DLTS,” Japanese Journal of Applied Physics, Vol. 58, No. SB, pp. SBBK02-1 - 4, (2019).
  3. (3) “Experimental evidence of trap level modulation in silicon nitride thin films by hydrogen annealing,” Japanese Journal of Applied Physics, Vol. 57, No. 6S3, pp. 06KB04-1 - 5, (2018).
  4. (4) "Physically unclonable function using initial waveform of ring oscillators on 65nm CMOS technology," Japanese Journal of Applied Physics, Vol. 56, No. 4, pp. 04CF13-1 - 4, (2017).
  5. (5) ”Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation,” IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 64, No. 4, pp. 462-466 (2017).
  6. (6) “Mechanism of gate dielectric degradation by hydrogen migration from the cathode interface,” Microelectronics Reliability, Vol. 70, pp. 12-21 (2017).
  7. (7) “Unified transient and frequency domain noise simulation for random telegraph noise and flicker noise using a physics-based model,” IEEE Transactions on Electron Devices, Vol. 61, No. 12, pp. 4197-4203 (2014).
  8. (8) "Extracting physically unclonable function from spin transfer switching characteristics in magnetic tunnel junctions," IEEE Transactions on Magnetics, Vol. 50, No. 11, Paper #: 3402004 (2014).
  9. (9) “Time-dependent dielectric breakdown (TDDB) distribution in n-MOSFET with HfSiON gate dielectrics under DC and AC stressing,” Microelectronics Reliability, Vol. 53, No. 12, pp. 1868-1874 (2013).
  10. (10) "Tunneling current modulation by Ge incorporation into Si oxide films for flash memory applications," Applied Physics Letters, Vol. 100, No. 7, Paper #: 72902 (2014).
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  2. (2) US9794073, Information processing system and semiconductor device
  3. (3) US9755064, Semiconductor device and method for manufacturing the same
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  5. (5) US9672103, Decoding device, decoding method, and memory system
Award Achievement Award in IEEE International Conference on IC Design & Technology (ICICDT-2017)
Recruitment of research assistant(s) No
Affiliated academic society (Membership type) (1)IEEE
(2)The Japan Society of Applied Physics
Education Field (Undergraduate level) Semiconductor Integrated Circuits
Education Field (Graduate level) Advanced Nano-electronics