Study at TCU


Name KUWAKO Masashi
Official Title Assistant Professor
Affiliation Computer Science
Profile My specialty is desgin of degital systems, especially asynchronous logic design.Asynchronous logic circuits have the advantages of low power consumption, high-speed operation, having a high affinity for high-speed devices.They are actually used in applications that require low power consumption, such as IC cards.I am particularly interested in the logic synthesis phase in the design flow of digital systems.
Since digital systems are constructed with a huge number of elements, design automation is also an important issue in logic synthesis research.I also develop design automation tools using C language and Perl scripts.
I am also interested in education of logic circuits at the undergraduate level.In recent years, student experiments on logic circuits are often conducted using hardware description languages(HDL), but it is difficult for beginners who have insufficient understanding of logic circuits to learn them through HDL.I am studying a method for conducting student experiments on computers in a way that makes it easier to Understand the operation of actual logic circuits than in a hardware description language.
Research Field(Keyword & Summary)
  1. (1) Asynchronous logic desgin

    The aim of this research is to establish a method for implementing a digital system by asynchronous logic design that does not use clock signals.Asynchronous logic circuits have the advantages of low power consumption, high-speed operation, having a high affinity for high-speed devices.

  2. (2) Design automation

    Design automation is important in the field of logic synthesis.The focus of this research is to develop software tools that automatically generate descriptions that express the actual circuit structure from source descriptions based on grammar that are easy for designers to understand intuitively.

Representative Papers
  1. (1) Yohei Karasawa, Masashi Kuwako, Toshihiro Niinomi, Takanori Yokoyama, "Design Method for a Interface Considering Circuit Performance in GALS Systems Based on Clock Gating", The IEICE transactions on information and systems (Japanese edition) 94(1), 324-333 (Jan. 2011)
  2. (2) A.Takamura, M.Kuwako, M.Imai, T.Fujii, M.Ozawa, I.Fukasaku, Y.Ueno, T.Nanya, "TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive Model", IEEE, Proceedings of International Conference on Computer Design(ICCD)'97 (Oct. 1997)
  3. (3) Takashi Nanya, Yoichiro Ueno, Hiroto Kagotani, Masashi Kuwako, Akihiro Takamura, "TITAC: Design of a Quasi-Delay-Insensitive Microprocessor", IEEE Design and Test of Computers, Vol.11 No.2, pp.50-63, IEEE, (1994)
  4. (4) Masashi Kuwako, Takashi Nanya, "Timing-reliability evaluation of asynchronous circuits based on different delay models", International Symposium on Advanced Research in Asynchronous Circuits and Systems, IEEE Computer Society, pp.22-31(Nov. 1994)
Grant-in-Aid for Scientific Research Support: Japan Society for Promotion of Science (JSPS)
Recruitment of research assistant(s) No
Affiliated academic society (Membership type) (1) IEICE(Member)
(2) IEEJ(Member)
Education Field (Graduate level) Logic circuits